Everyone is looking at the scoreboard wrong. The mainstream narrative treats SMIC scaling up older node capacity as a masterstroke of defensive maneuvering against export controls. That is a fantasy cooked up by PR departments and repeated by analysts who haven't set foot in a cleanroom in a decade.
I have watched companies burn nine-figure budgets on redundant mature-node lines because middle management needed a win to show executive leadership. SMIC adding more 28nm and 40nm capacity while the rest of the world races toward gate-all-around architectures and sub-2nm nodes is not aggressive positioning. It is an expensive retreat disguised as a charge.
Let us dismantle the lazy consensus piece by piece.
The Maturity Trap
The lazy consensus says that AI needs chips, chips need silicon, and therefore any silicon foundry expanding output is printing money. This ignores a fundamental economic reality of semiconductor manufacturing: volume on obsolete nodes does not solve structural supply chain bottlenecks for high-end artificial intelligence workloads.
AI accelerators demand extreme transistor density, high-bandwidth memory integration, and advanced packaging techniques like CoWoS. Pumping out millions of legacy microcontrollers, power management integrated circuits, and basic display drivers does not feed the machine learning beast.
When analysts point to surging demand for mature nodes, they conflate consumer electronics inventory restocking with secular artificial intelligence infrastructure growth. They are entirely different ecosystems.
The Cost of Captive Manufacturing
Building a fabrication plant requires staggering capital expenditure. When you throw billions at mature process technology lines that face structural pricing pressure from fierce domestic and global competition, your return on invested capital moves in one direction: down.
I have seen state-backed operations prioritize capacity metrics over unit economics. They measure success by square footage of cleanroom space and wafer starts per month. Those are vanity metrics. If you are producing silicon that the market only wants at a razor-thin margin, scaling up production simply accelerates your cash burn.
[Legacy Node Capacity] ---> [Oversaturated Market] ---> [Margin Compression] ---> [Capital Drain]
The Export Control Paradox
Washington thought restricting extreme ultraviolet lithography access would halt high-end progress. They were right about the ceiling, but they accidentally created a floor of misplaced optimism.
Because advanced nodes are heavily restricted, capital has flooded into legacy nodes. This created a localized supply glut in China for standard components while locking producers out of the architectural shifts that actually matter for next-generation intelligence platforms.
Imaging a scenario where every regional player builds out redundant 28nm capacity just to secure domestic supply chains. You end up with localized overcapacity, cratering spot prices, and a massive misallocation of engineering talent that should be focused on domestic equipment development, materials science, and chiplet architectures.
The Real Bottleneck is Not Capacity
People keep asking: "Can SMIC produce enough chips to satisfy domestic demand?"
That is the wrong question.
The real question is: "Can SMIC produce chips that do not require architectural compromises so severe that training large language models becomes economically unviable?"
The answer is no. Without extreme ultraviolet tools and advanced packaging ecosystems, trying to brute-force AI workloads on legacy hardware scales up energy consumption and latency to unacceptable thresholds. You can stack as many older processors together as you want, but the interconnect overhead will strangle your training speeds.
The Uncomfortable Truth About Yields
Let us talk about what happens behind closed doors during rapid expansion cycles. When political pressure dictates aggressive capacity growth, quality control takes a back seat.
Ramping up wafer starts without mature tooling ecosystems leads to yield degradation. If your defect density creeps up by even a fraction of a percentage point on large-die processors, your effective output of usable silicon plummets.
The market hears "expansion" and thinks "growth." Operators know that expansion without yield stability equals scrap silicon.
What You Should Do Instead
If you are deploying capital based on the assumption that mature-node foundry expansion is a proxy for AI market health, stop immediately.
- Audit your supply chain exposure: Separate basic semiconductor components from high-value compute infrastructure.
- Ignore headline capacity numbers: Total wafer starts mean nothing if the product mix cannot run modern workloads efficiently.
- Watch the equipment supply chain: The real tell is not how many fabs open, but whether domestic lithography and metrology alternatives can clear the physics hurdles of sub-7nm production.
Stop betting on the noise. Look at the physics.
